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| 8V 2W GaAs Power Amplifier Die (4.5 - 7.1 GHz) ITT6401D FEATURES * * * * * * * * Broadband Performance High Linear Power (P1dB): 33 dBm typical High Power Added Efficiency: 40% typical at P1dB High Linear Gain: 18 dB typical Efficient performance with 3 to 10 Volt power supply 50 Input/Output Impedance Self-Aligned MSAG(R) MESFET Process Unconditionally stable DESCRIPTION The ITT6401D is a two stage MMIC power amplifier fabricated on GaAsTEK's mature GaAs Self-Aligned MSAG (R) MESFET Process. This product is fully matched to 50 ohms on both the input and the output and can be used as either a driver or an output stage amplifier. Although it can be used for several different applications, it is ideally suited for VSAT and ISM applications. MAXIMUM RATINGS (TA = 25 C unless otherwise noted) Rating DC Drain Supply Voltage DC Gate Supply Voltage RF Input Power Junction Temperature (See maximum operating temperature chart in Fig. 5) Symbol VDD VGG PIN TJ TSTG Value 12V -4V 200 +175 -40 to +175 Unit Vdc Vdc mW C C Storage Temperature ELECTRICAL CHARACTERISTICS VDD=8.0 V, IDQ=360 mA, PIN=18 dBm, TA=25 C Characteristic Frequency Load Power Power Gain Power Gain Variation Over Frequency Power Added Efficiency Drain Current Gate Bias Voltage (No RF Input) Gate Current Input VSWR Harmonics (=5.5 GHz, POUT=34 dBm) Thermal Resistance (Junction of 2nd stage FET to TCARRIER, Note 1) Noise Figure Third-Order Intercept Point (IDQ=525 mA) Stability (PIN= 5 to 20 dBm, VDD=3 to 10 V, Load VSWR = 3:1) Symbol POUT GP IDS VGG IGG 2 3 RTH NF TOI -- Min 4.5 33 15 39 -3.1 -4 Typ 34 16 1 47 660 -2.1 1 2.1:1 -25 -27 20 8.8 43 Max 7.1 1.5 -1.1 4 3:1 -20 -23 Unit GHz dBm dB dB % mA V mA dBc dBc C/W dB dBm All non-harmonically related outputs more than 70dB below desired signal Note 1: RTH includes the thermal resistance between the bottom of the die and the carrier, assuming the die attachment guidelines on page 3 are followed. The second stage FET determines the overall thermal performance. Therefore, when performing thermal calculations, the dissipated power needs only to be nd calculated for the amplifier's 2 stage. Specifications Subject to Change Without Notice 901972 D, February 1999 GaAsTEK 5310 Valley Park Drive Roanoke, VA 24019 USA www.gaastek.com Tel: 1-540-563-3949 1-888-563-3949 (USA) Fax: 1-540-563-8616 1 8V 2W GaAs Power Amplifier Die (4.5 - 7.1 GHz) ITT6401D TYPICAL CHARACTERISTICS 50 45 PAE 5:1 (dBm) and PAE (%) 6:1 50 45 40 35 30 25 20 15 10 5 POUT PAE (dBm) PAE (%) 40 35 30 25 20 15 10 5 0 3 4 5 6 Frequency (GHz) 7 8 VSWR POUT 4:1 3:1 2:1 1:1 Input VSWR OUT OUT 0 4 6 8 10 12 14 16 PIN , Input Power (dBm) 18 20 Figure 1. Output power, efficiency, and input VSWR vs. frequency Conditions for Figure 1: VDD = 8V, IDQ = 360 mA (no RF), PIN = 18 dBm Figure 2. Output power and efficiency vs. input power Conditions for Figure 2: VDD = 8V, IDQ = 360 mA (no RF), = 5.5 GHz 50 45 (dBm) and PAE (%) 40 35 30 25 20 15 10 5 0 3 4 5 6 7 8 VDD, Supply Voltage (V) 9 10 POUT PAE P OUT , Output Power (dBm) 40 35 30 25 20 15 10 5 0 -5 -10 -15 -20 2 3 OUT fo=5.5 GHz fo=7.0 GHz Figure 3. Output power and efficiency vs. supply voltage Conditions for Figure 3: IDQ = 360 mA (no RF), PIN = 18 dBm, = 5.5 GHz Figure 4. Harmonics Conditions for Figure 4: VDD = 8V, IDQ = 360 mA (no RF), PIN = 18 dBm Specifications Subject to Change Without Notice 901972 D, February 1999 GaAsTEK 5310 Valley Park Drive Roanoke, VA 24019 USA www.gaastek.com Tel: 1-540-563-3949 1-888-563-3949 (USA) Fax: 1-540-563-8616 2 8V 2W GaAs Power Amplifier Die (4.5 - 7.1 GHz) ITT6401D APPLICATION INFORMATION PDISS2, Dissipated Pwr in 2nd Stage (W) 7.0 6.0 5.0 Slope = -1/RTH 4.0 3.0 2.0 1.0 0.0 0 25 50 75 100 125 150 175 200 TCARRIER, Temperature at Carrier (C) Conditions for Figure 5. * PDISS2 = IDD2*VDD - POUT, which refers to the dissipated power in the hottest area of the die (Stage 2 FET) * IDD2 is the supply current consumed by the second stage FET and is typically 80% of IDD. Figure 5. Maximum operating temperature List of components: C1 thru C8 = 100pF single layer ceramic chip capacitor C9 = C11 = 0.1 uF ceramic chip capacitor C10 = C12 = 5000 pF capacitor Assembly: Chip dimensions: 4.4mm x 3.4mm, .003" thickness. Die attach: Use AuSn (80/20) 1 mil. preform solder. Limit time @ 300 C to less than 5 minutes. Wirebonding: Bond @ 160 C using standard ball or thermal compression wedge bond techniques. For DC pad connections, use either ball or wedge bonds. For best RF performance, use wedge bonds of shortest length, although ball bonds are also acceptable. Biasing: 1. User must apply negative bias to VGG before applying positive bias to VDD to prevent damage to amplifier. 2. Nominal bias is IDQ=360mA (10% IDSS) at +8.0 Volts on VDD. This requires a typical VGG bias of -2.1 Volts (no RF input drive). 50 50 Figure 6. Bonding diagram Specifications Subject to Change Without Notice 901972 D, February 1999 GaAsTEK 5310 Valley Park Drive Roanoke, VA 24019 USA www.gaastek.com Tel: 1-540-563-3949 1-888-563-3949 (USA) Fax: 1-540-563-8616 3 |
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